Power and area efficient clock stretching and critical path reshaping for error resilience

Process, voltage and temperature variations are on the rise with technology scaling. Nano-scale technology requires huge design margins to ensure reliable operation. Worst case design margining consumes significant amount of circuits and systems resources. In-situ error detection or correction is an alternative method for cost effective variation tolerance. However, existing in-situ error detection and correction circuits are power and area hungry since they use speculative error management, which gives less power savings at higher error rates. This paper proposes an error resilience technique utilizing available slack in the design. The proposed method uses a clock stretching circuit to relax timing margins on selected critical paths that has sufficient consecutive stage slack. We also propose a power optimization method which reshapes the critical path logic proportionate to the consecutive stage slack. Experimental results show that the proposed method achieves the power and area savings of 40% and 8% respectively compared to the worst case design approach. When compared to the TIMBER error resilience approach, the proposed method saves power more than 74% and area more than 13% at design time. Document type: Articl

Design of variation-tolerant integrated circuits

The semiconductor industry is strategically focusing on automotive markets and significant investment is targeted to address these markets. Run time better-than-worst-case designs like Razor leads to massive timing errors upon breaching the critical operating point and have significant area overheads. As we scale to higher-reliability automotive and industrial markets we need alternative techniques that will allow full extraction of the power benefits without sacrificing reliability. In this work, we propose four resilient processor subsystems which incorporate slack balancing circuits to relax the timing margins of a processor pipeline based on the available slack. Together with logic under-design, the proposed methodology results in power and area savings compared to worst-case design techniques. The presence of slack balancing circuits ensures correct functionality of the design at worst operating conditions. Based on this, we propose the first subsystem to utilize positive slack available in the pipeline stages using Slack Balancing Flip-flops (SBFFs) and re-distributes it to the preceding error-prone critical paths. SBFF has a redundant latch to sample the late arriving data. We reshape the SBFF fan-in cone by downsizing the logic to achieve power and area savings of 12% and 8%, respectively, as compared to the worst-case design. Our second subsystem uses library based power optimization techniques together with SBFFs. Here we prune the SBFF standard cell library to filter out the power-hungry cells. In addition to this, we use Better than Worst-case (BTWC) sigma corner library to under-design the logic whose slack margins are relaxed by the SBFFs. This gave a power and area savings of 47% and 3%, respectively, in the execute pipeline stage. The third subsystem provides a Clock Stretching Flip-flop (CSFF) to remove the redundancy inside SBFFs for better power and area savings. The combination of CSFFs, multi-bit flip-flops (MBFFs), logic reshaping and BTWC sigma corner libraries resulted in a power and area savings of 32% and 16%, respectively, in the fetch pipeline stage and 69% and 15%, respectively, in the execute pipeline stage when compared to the traditional worst-case design. In the fourth subsystem, we use Data-dependent Clock Stretching Flip-flop (DDCSFF) in addition to simple CSFFs to replace the critical endpoints with sufficiently low activity rates. Here we use logic reshaping for power optimization together with CSFFs and DDCSFFs. Experiment results showed power and area savings of 70% and 9.5%, respectively, in the execute pipeline stage with respect to the worst-case design. For all the proposed subsystems, the critical logic power minimization method relaxes the slack margins of all the timing paths including the short paths converging into the SBFF. The timing budgeting and timing correction using opportunistic slack eliminates critical operating point behaviour, meta-stability issues and hold buffer overheads encountered in existing resilience techniques.Doctor of Philosophy (EEE

Photocrosslinking of azidated poly(vinyl chloride) coated onto plasticized PVC surface: route to containing plasticizer migration

The migration of phthalate esters which are commonly employed for plasticizing poly(vinyl chloride) (PVC) is a significant problem in PVC-based medical devices as well as in packaging used for food stuffs and pharmaceuticals. Medical-grade PVC resin was treated with sodium azide in dimethylformamide (DMF) to prepare the azide polymer. The polymeric azide was coated onto the surface of plasticized PVC sheets by dipping in a solution of the polymer in tetrahydrofuran (THF). Crosslinking of the azide polymer was accomplished by irradiating the surface using a 125 W UV lamp for various lengths of time. Migration of the plasticizer di 2-(ethylhexyl phthalate) (DEHP) from coated and uncoated samples was examined in n-hexane at 30°C. It was found that 50-80% reduction in migration of DEHP could be effected from plasticized PVC in comparison with the controls in 72 h by this technique depending on the concentration of the coating solution, coating thickness, azide concentration, and irradiation dose

Opportunistic design margining for area and power efficient processor pipelines in real time applications

The semiconductor industry is strategically focusing on automotive markets, and significant investment is targeted to addressing these markets. Runtime better-than-worst-case designs like Razor lead to massive timing errors upon breaching the critical operating point and have significant area overheads. As we scale to higher-reliability automotive and industrial markets we need alternative techniques that will allow full extraction of the power benefits without sacrificing reliability. The proposed method utilizes positive slack available in the pipeline stages and re-distributes it to the preceding critical logic stage using Slack Balancing Flip-Flops (SBFFs). We use opportunistic under designing to get rid of the area, power and error correction overheads associated with the speculative hardware of runtime techniques. The proposed logic reshaping results in 12 percent and eight percent power and area savings respectively compared to the worst-case design approach. Compared to runtime better-than-worst-case designs, we get 51 percent and 10 percent power and area savings, respectively. In addition, the timing budgeting and timing correction using opportunistic slack eliminate critical operating point behavior, metastability issues and hold buffer overheads encountered in existing runtime resilience techniques.Published versio

Power and Area Efficient Clock Stretching and Critical Path Reshaping for Error Resilience

Energy efficient semiconductor chips are in high demand to cater the needs of today’s smart products. Advanced technology nodes insert high design margins to deal with rising variations at the cost of power, area and performance. Existing run time resilience techniques are not cost effective due to the additional circuits involved. In this paper, we propose a design time resilience technique using a clock stretched flip-flop to redistribute the available slack in the processor pipeline to the critical paths. We use the opportunistic slack to redesign the critical fan in logic using logic reshaping, better than worst case sigma corner libraries and multi-bit flip-flops to achieve power and area savings. Experimental results prove that we can tune the logic and the library to get significant power and area savings of 69% and 15% in the execute pipeline stage of the processor compared to the traditional worst-case design. Whereas, existing run time resilience hardware results in 36% and 2% power and area overhead respectively